1. Field of the Invention
This invention relates to dynamic circuits and more particularly to keeper devices utilized in dynamic circuits.
2. Description of the Related Art
Dynamic Complementary Metal Oxide Semiconductor (CMOS) circuits precharge a node and conditionally discharge the node based on inputs evaluated by the circuit. Referring to FIG. 1, a prior art OR circuit 100 is illustrated with a p-channel precharge device 102 and n-channel evaluation logic. The n-channel evaluation logic includes devices 104–108 and an n-channel ground switch 110. Devices 102 and 110 are enabled during opposite phases of the signal CLOCK, disabling at least one transistor in the path between VDD and VSS at a given time. Therefore, a DC current path does not exist from VDD to VSS and the steady-state current is zero. However, a static leakage current exists due to reverse bias leakage between diffusion regions and the substrate in the n-channel devices 104–110. This leakage current may sufficiently discharge dynamic node 116 to produce an incorrect value at the output node, OUT.
The effects of this leakage current may be countered by introducing keeper 112 at dynamic node 116. Keeper 112 latches the output of the circuit. Alternatively, keeper 112 could be statically configured by grounding the gate input. Keeper 112 is a weak keeper, that is, a p-transistor designed to have a low gain achieved by a small W/L ratio so that the gain is low enough to be overcome by pull-down transistors 104–110. However, keeper 112 has a large enough gain to offset the effects of the leakage current. In circuits with a large number of inputs, each input requiring a pull-down transistor coupled to a single dynamic node, the leakage current may be too large for a weak keeper to counteract. Replacing the weak keeper of keeper 112 with a strong keeper (i.e., a device that has a high gain achieved by a large W/L ratio), slows down circuit transitions due to the additional capacitance of the stronger keeper transistor. In addition, pull-down devices may be unable overcome the strong keeper transistor and the dynamic node may not switch properly, resulting in the circuit producing incorrect output values at the output node. Instead, prior art circuits typically maintain proper functionality and high speed by limiting the number of pull-down transistors used with a weak keeper. The limit on the number of pull-down transistors may limit the number of inputs the dynamic circuit can evaluate. For example, in FIG. 1, circuit 100 is limited to k input pull-down devices. As a result, circuit designs using these dynamic circuits may implement more complex circuitry to achieve the same functionality as a device having a greater number of input pull-down devices. Increasing circuit complexity may decrease speed, increase circuit size, and increase manufacturing costs.
Therefore, it would be desirable to use a strong keeper to overcome leakage of the evaluation devices of a large number of inputs, without compromising the functionality or speed of the circuit.